1. Field of the Invention
The various embodiments described herein relate to a system for performing a serial communication between a central control block and satellite components according to the appended claims.
2. Description of the Related Art
A microprocessor chip comprises various parts that must be configured or monitored during a power-on-reset (POR) procedure or even while the microprocessor chip is running.
A general structure implements a central control block that connects to distributed satellite components in a ring fashion to minimize routing overhead. The satellite components aid such a structure in obeying protocols and performing direct accesses to or from registers.
An access to the central control block can be requested from one or several internal masters and external masters. The internal masters are arranged within the chip. The external masters are arranged outside of the chip. Typical examples of internal masters include the POR engine or the processor core itself. A service processor acting as an external master accesses the central control block via protocols such as JTAG (Joint Test Action Group), I2C (Inter-Integrated Circuit), or proprietary protocols.
U.S. Pat. No. 6,529,979 describes a method and an apparatus for transferring data using an on-chip bus. A data transaction consists of an address packet and a data packet. The address packet and the data packet are transmitted on the on-chip bus. The on-chip bus is a two-wire serial bus consisting of an address line and a data line. The on-chip bus connects a plurality of satellite components in a daisy-chain fashion to a central source. Each satellite component on the chip is associated with a unique identifier. In response to a determination that the data transaction is accepted by the satellite component, the address packet is modified to indicate the acceptance of the address packet and the data packet. The acceptance is determined by the address in the address packet positively comparing to the unique identifier for the satellite component.
In this prior art a satellite component may experience a write error or a read error. For example, this may occur in a hang situation. Such a hang situation is detected by implementing a timer in each satellite component. In the event of a hang situation, a satellite component reports an error to another logic part of the processor (such logic part is outside of the scope of the various embodiments described herein). However, it is not possible to relate the reported error to the register access causing the error if the central source has carried out other register accesses in the meantime.